Logic operation circuits having the same logic operation characteristics typically consume more power at higher supply voltage levels than at lower supply voltage levels. If a signal having a high voltage level is input to a logic operation circuit and the logic operation circuit is driven at such a high voltage level, the logic operation circuit may consume more power than if it is driven at a lower voltage level. In order to solve this problem, an input buffer circuit may be used to lower the voltage level of the signal input to the logic operation circuit so that the logic operation circuit is driven at a voltage level lower than the voltage level of the signal input thereto.
A semiconductor device may be driven using one or two voltage sources. In a case where there is the need to supply various levels of voltages, to the semiconductor device, a voltage regulator may be used to generate the various levels of voltages. Thus, a manufacturer of the semiconductor device may manufacture the semiconductor device in consideration of the highest one of the voltages provided by the voltage sources.
FIG. 1 is a circuit diagram of a conventional input buffer circuit 100. Referring to FIG. 1, the conventional input buffer circuit 100 includes a buffering block 120, a level shifter 130, and a buffer 140. The buffering block 120 includes a NAND gate 121, which receives a signal input to a semiconductor device via a pad 110 with one of its input ports, and a first inverter 123, which inverts a signal output from the NAND gate 121. A low power mode signal STD is input to the other input port of the NAND gate 121. The low power mode signal STD is not enabled when the semiconductor device normally operates but is enabled when the semiconductor device stops operating. When the low power mode signal STD is enabled, the buffering block 120 outputs a uniform level of direct current (DC) voltage. Here, it is assumed that the input signal swings between a first power supply voltage VDD3 and a ground voltage or between the first power supply voltage VDD3 and a voltage lower than the ground voltage. In FIG. 1, MV indicates that an element operates at a high voltage level.
The level shifter 130 receives the input signal from the buffering block 120 and lowers the voltage level of the input signal in consideration of a second power supply voltage VDD that drives a logic circuit 150 of the semiconductor device. The buffer 140 enhances the driving capability of a signal output from the level shifter 130. The same level of power supply voltage is applied to the buffer 140 and to the logic circuit.
The logic circuit 150 is driven using the second power supply voltage VDD, which is lower than the first power supply voltage VDD3, in order to reduce the power consumption of the semiconductor device. A manufacturer of the semiconductor device applies the first power supply voltage VDD3 to the semiconductor device and generates the second power supply voltage VDD, which is lower than the first power supply voltage VDD3, in the semiconductor device using a voltage regulator.
The conventional input buffer circuit 100 is designed in consideration of the assumption that the input signal swings within a predetermined range of the first power supply voltage VDD3. However, the level shifter 130 should be used even when the input signal swings within a range of the second power supply voltage VDD.